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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16314-2E
32-Bit Microcontroller
CMOS
FR60 MB91307 Series
MB91306R/MB91307R
DESCRIPTION
The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, high-speed CPU processing. External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are provided for high-speed execution of CPU instructions. This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX and printer control that demand high-capability CPU processing power. The MB91307 series is a FR60 family product based on the FR30/40 family CPU with enhanced bus access for higher speed operation.
FEATURES
FR CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * Operating frequency 66MHz [with PLL: base frequency 16.5 MHz] * 16-bit fixed length instructions (basic instructions), 1 instruction per cycle * Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc. * Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions (Continued)
PACKAGE
120-pin, plastic LQFP
(FPT-120P-M21)
MB91307 Series
* Easier assembler notation: register interlock function * Built-in multiplier/instruction level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (PC, PS removal): 6 cycles, 16 priority levels * Harvard architecture for simultaneous execution of program access and data access * CPU hold 4-word queue allows advanced instruction fetch function * 4G bytes expanded memory space enables linear access * Instruction compatible with FR30/40 family Bus Interface * Operating frequency: Max 33 MHz * 8- or 16-bit data output * Built-in pre-fetch buffer * Unused data/address pins can be used as general-0purpose input/output ports * Fully independent 8-area chip select outputs, can be set in minimum 64K bytes units * Interface support for many memory types SRAM, ROM/Flash Page mode flash ROM, page mode ROM interface Burst mode flash ROM (select burst length 1, 2, 4, 8) * Basic bus cycle: 2 cycles * Programmable by area with automatic wait cycle generation to enable wait insert * RDY input for external wait cycles * DMA supports fly-by transfer with independent I/O wait control Built-in RAM * 128K bytes (MB91307R), 64K bytes (MB91306R) * Accepts writing of data and instruction codes, enabling use as instruction RAM Instruction cache * 1K bytes capacity * 2-way set associative * 4-words (16 bytes) per set * Lock function enables permanent program storage * Areas not used for instruction cache can be used for RAM DMAC (DMA controller) * 5-channel (3-channel external-to-external) * 3 transfer sources (external pin, internal peripheral, software) * Addressing mode with 32-bit full address indication (increment, decrement, fixed) * Transfer mode (demand transfer / burst transfer / step transfer / block transfer) * Fly-by transfer support (3 channels between external I/O and external memory) * Transfer data size selection 8/16/32-bit Bit search module (using REALOS) * Searches words from MSB for first bit position of a 1/0 change Reload timer (includes 1 channel for REALOS) * 16-bit timer: 3 channels * Internal clock multiplier choice of x2, x8, x32 (Continued)
2
MB91307 Series
(Continued) UART * Full duplex double buffer * 3-channel * Parity/no parity selection * Asynchronous (start-stop synchronized), CLK-synchronized communications selection * Built-in exclusive baud rate timer * External clock can be used as transfer clock * Variety of error detection functions (parity, frame, overrun) I2C* interface * Master/slave sending and receiving * Arbitration function * Clock synchronization function * Slave address/general call address detection function * Transfer direction detection function * Start condition repeat generator and detection function * Bus error detection function * 10-bit/7-bit slave address * Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps) Interrupt controller * Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0 * Interrupt from internal peripheral devices * Programmable priority settings (16 levels) enabled, except for non-maskable interrupt * Can be used for wake-up from stop mode A/D converter * 10-bit resolution, 4-channel * Sequential comparator type, conversion time approx. 5.4 s * Conversion modes: single conversion mode, continuous conversion mode * Startup source: software / external trigger / timer output signal Other interval timers * 16-bit timer with 3 channels (U-timer) * Watchdog timer I/O port * Maximum 69 ports Other features * Built-in oscillator circuit for clock source, PLL multiplier selection enabled * INIT reset pin * Also included: watchdog timer reset, software reset * Power-saving modes: stop mode, sleep mode supported * Gear functions * Built-in time base timer * Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R : MB91V307R (Evaluation products) * CMOS technology : 0.25 m : MB91V307R, 0.18 m : MB91306R, MB91307R * Supply voltage : MB91V307R : 3.3 V 0.3 V (built-in regulator 3.3 V 2.5 V) : MB91306R, MB91307R : 3.3 V 0.3 V, 1.8V 0.15 V dual power supplies
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 3
MB91307 Series
PIN ASSIGNMENT
PA2/CS2 PA1/CS1 PA0/CS0 PB7/IORD PB6/IOWR VCC X0 X1 VSS PB5/DEOP1/DSTP1 PB4/DACK1 PB3/DREQ1 PB2/DEOP0/DSTP0 PB1/DACK0 PB0/DREQ0 MD2 MD1 MD0 PG2/DEOP2/DSTP2 PG1/DACK2 PG0/DREQ2 PH7/SCL PH6/SDA PH5/TOT2 PH4/TOT1 PH3/TOT0 VSS PH2/SC2 PH1/SO2 PH0/SI2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
* : "L" level output after initialization and reset
4
P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
PA3/CS3 PA4/CS4 PA5/CS5 VCCI PA6/CS6 PA7/CS7 P80/RDY P81/BGRNT P82/BRQ RD UUB/WR0 P85/ULB/WR1 NMI VCCI VSS INIT P90/SYSCLK P91 P92/MCLK P93 P94/LBA/AS P95/BAA P96 P97/WE P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21
PI5/SC1 PI4/SO1 PI3/SI1 PI2/SC0 PI1/SO0 PI0/SI0 VCC PJ7/INT7/ATG PJ6/INT6/TIN2 PJ5/INT5/TIN1 PJ4/INT4/TIN0 PJ3/INT3 PJ2/INT2 PJ1/INT1 PJ0/INT0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/P70 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61
FPT-120P-M21
MB91307 Series
PIN DESCRIPTIONS
Pin no. Pin name D16 to D23 P20 to P27 93 to 100 102 to 109 111 to 118 120, 1 to 7 8 9 10 11 12 to 15 D24 to D31 A00 to A07 A08 to A15 A16 to A23 P60 to P67 A24 P70 AVCC AVRH AVSS/AVRL AN0 to AN3 INT0 to INT3 PJ0 to PJ3 TIN0 to TIN2 20 to 22 INT4 to INT6 PJ4 to PJ6 ATG 23 INT7 PJ7 SI0 PI0 SO0 26 PI1 F I I C F F F F D I/O circuit type C Description External data bus bit 16 to bit 23 Valid only in external bus 16-bit mode. These pins can be used as ports in external bus 8-bit mode External data bus bit 24 to bit 31 External address output bit0 to bit7 External address output bit8 to bit15 External address output bit16 to bit23 These pins can be used as ports according to setting External data bus output bit24 This pin can be used as a port according to setting Power supply pin. Analog power supply for A/D converter A/D converter reference voltage supply Power supply pin. Analog power supply for A/D converter A/D converter reference voltage supply. Analog input pin. External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally General purpose input/output port Reload timer input. When the corresponding timer input is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port A/D converter external trigger input. When selected as an A/D start source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port UART0 data input. When the UART0 channel is in input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. UART0 data output. This function is valid when the UART0 data output function setting is disabled. General purpose input/output port. This function is valid when the UART0 data output function setting is disabled. (Continued) 5
85 to 92
16 to 19
I
25
F
MB91307 Series
Pin no.
Pin name SC0
I/O circuit type
Description UART0 clock output. The clock output is valid when the UART0 clock output function setting is enabled. General purpose input/output port. This function is valid when the UART0 clock output function is disabled. UART1 data input. When UART1 is set for input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. UART1 data output. This function is enabled when the UART1 data output function setting is enabled. General purpose input/output port. This function is valid when the UART1 data output function setting is disabled. UART1 clock input/output. The clock output is enabled when the UART1 clock output function setting is enabled. General purpose input/output port. This function is valid when the UART1 clock output function setting is disabled. UART2 data input. When UART2 is set for input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. UART2 data output. This function is enabled when the UART2 data output function setting is enabled. General purpose input/output port This function is enabled when the UART2 data output function setting is disabled. UART2 clock input/output. The clock output is enabled when the UART2 clock output function setting is enabled. General purpose input/output port This function is enabled when the UART2 clock output function is disabled. Timer output port. This function is valid when the timer output setting is enabled. General purpose input/output port.This pin outputs an "L" level signal at reset. Timer output port. This function is valid when the timer output setting is enabled. General purpose input/output port.This pin outputs an "L" level signal at reset. Timer output port. This function is valid when the timer output is enabled. General purpose input/output port. (Continued)
27 PI2 SI1 PI3 SO1 29 PI4 SC1 30 PI5 SI2 PH0 SO2 32 PH1 SC2 33 PH2 TOT0 35 PH3 TOT1 36 PH4 37 TOT2 PH5
F
28
F
F
F
31
F
F
F
C
C
C
6
MB91307 Series
Pin no.
Pin name SDA PH6 SCL PH7 DREQ2 PG0 DACK2
I/O circuit type
Description I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z level. When the I2C bus is in use, this is an open drain pin. General purpose input/output port. I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z level. When the I2C bus is in use, this is an open drain pin. General purpose input/output port. DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. General purpose input/output port. This function is valid when the DMA transfer request acknowledge output setting is enabled. DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled.
38
Q
39
Q
40
F
41 PG1 DEOP2 42 DSTP2 PG2 43 to 45 MD2 to MD0 DREQ0 PB0 DACK0 47 PB1 DEOP0 48 DSTP0 PB2
F
F
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled.
G
Mode pins 2 to 0. The setting of these two pins determines the basic operating mode. They should be connected to Vcc or Vss. DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. General purpose input/output port. This function is enabled when the DMA transfer request acknowledge output setting is disabled. DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled.
46
F
F
F
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled. (Continued)
7
MB91307 Series
Pin no.
Pin name DREQ1 PB3 DACK1
I/O circuit type
Description DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. General purpose input/output port. DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. General purpose input/output port. This function is enabled when the DNA transfer request acknowledge output setting is disabled. DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled.
49
F
50 PB4 DEOP1 51 DSTP1 PB5 53 54 X1 X0 IOWR 56 PB6 IORD 57 PB7 CS0 58 PA1 CS1 59 PA1 CS2 60 PA2 CS3 61 PA3
F
F
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled.
A
Clock (oscillator) output Clock (oscillator) input Write strobe output for DMA fly-by transfer. This function is valid when the DMA fly-by transfer write strobe output setting is enabled. General purpose input/output port. This function is valid when the DMA fly-by transfer write strobe output setting is disabled. Read strobe output for DMA fly-by transfer. This function is valid when the DMA fly-by transfer read strobe output setting is enabled. General purpose input/output port. This function is valid when the DMA fly-by transfer read strobe output setting is disabled. Chip select output. This function is valid when the chip select 0 output setting is enabled. General purpose input/output port. This function is valid when the chip select 0 output setting is disabled. Chip select output. This function is valid when the chip select 1 output setting is enabled. General purpose input/output port. This function is valid when the chip select 1 output setting is disabled. Chip select output. This function is valid when the chip select 2 output setting is enabled. General purpose input/output port. This function is valid when the chip select 2 output setting is disabled. Chip select output. This function is valid when the chip select 3 output setting is enabled. General purpose input/output port. This function is valid when the chip select 3 output setting is disabled. (Continued)
F
F
F
F
F
F
8
MB91307 Series
Pin no.
Pin name CS4
I/O circuit type
Description Chip select output. This function is valid when the chip select 4 output setting is enabled. General purpose input/output port. This function is valid when the chip select 4 output setting is disabled. Chip select output. This function is valid when the chip select 5 output setting is enabled. General purpose input/output port. This function is valid when the chip select 5 output setting is disabled. Internal Power supply pin (1.8 V power supply) . Chip select output. This function is valid when the chip select 6 output setting is enabled. General purpose input/output port. This function is valid when the chip select 6 output setting is disabled. Chip select output. This function is valid when the chip select 7 output setting is enabled. General purpose input/output port. This function is valid when the chip select 7 output setting is disabled. External ready signal input. This function is valid when the external ready input setting is enabled. General purpose input/output port. This function is valid when the external ready input setting is disabled. External bus open acknowledge output. This pin outputs an L level signal when the external bus is open. This function is valid when the output setting is enabled. General purpose input/output port. This function is valid when the output setting is disabled. External bus open request input. The input value is "1" when the external bus is open. This function is valid when the input setting is enabled. General purpose input/output port. This function is valid when the input setting is disabled. External bus read strobe output. External bus write strobe output. Upper side of the 16-bit SRAM input/output mask enable signal. It is valid when the external bus is set to SRAM use. (WE/P97 function as the write strobe.) External bus write strobe output. Lower side of the 16-bit SRAM input/output mask enable signal. It is valid when the external bus is set to SRAM use. (WE/P97 function as the write strobe.) General purpose input/output port. This function is valid when the enable output setting is disabled. (Continued)
62 PA4 CS5 63 PA5 64 VCCI CS6 65 PA6 CS7 66 PA7 RDY 67 P80 BGRNT 68 P81 BRQ 69 P82 70 71 RD WR0 UUB
F
F F
F
C
F
P
M F
72
WR1 ULB P85
F
9
MB91307 Series
(Continued) Pin no. 73 74 76 Pin name NMI VCCI INIT SYSCLK 77 P90 78 P91 MCLK 79 P92 80 P93 AS 81 LBA P94 BAA 82 P95 83 P96 WE 84 P97 9 10 11 24, 55, 110 34, 52, 75, 101 AVCC AVRH AVSS/AVRL VCC VSS F F F F F F I/O circuit type H H B NMI request input Internal Power supply pin(1.8 V power supply) External reset input System clock output. This function is valid when the system clock output setting is enabled. The clock signal output is at the same frequency as the external bus operating frequency. Clock output halts in the stop mode or the hardware standby mode. General purpose input/output port. This function is enabled when the system clock output setting is disabled. General purpose input/output port. This function is enabled when the SDRAM clock enable output setting is disabled. Memory clock output. Clock output halts in the sleep mode, the stop mode or the hardware standby mode. General purpose input/output port. This function is enabled when the clock output setting is disabled. General purpose input/output port. This function is enabled when the SDRAM clock re-input setting is disabled. Address strobe output. This function is valid when the address strobe output setting is disabled. Burst flash ROM address load output. This function is valid when the address load output setting is enabled. General purpose input/output port. This function is valid when the address load output and address strobe output settings are disabled. Burst flash ROM address advance output. This function is valid when the address advance output setting is enabled. General purpose input/output port. This function is valid when the address advance output and column address strobe output settings are disabled. General purpose input/output port. This function is enabled when the column address strobe output setting is disabled. Write strobe output for 16-bit SRAM. This function is enabled when the write strobe output setting is enabled. General purpose input/output port. This function is enabled when the write strobe output setting is prohibited. A/D converter power supply A/D converter power supply A/D converter power supply (GND) Power supply pins Power supply pins (GND) Description
10
MB91307 Series
I/O CIRCUIT TYPE
Type
X1
clock input
Circuit
Remarks * Oscillator feedback resistance approx. 1 M
X0
A
STANDBY CONTROL
* CMOS hysteresis input with pull-up resistance (25 k)
B
digital input
* CMOS level input/output with standby control
digital output
C
digital output
digital input
STANDBY CONTROL
* Analog input with switch
D
analog input
CONTROL
(Continued)
11
MB91307 Series
Type
Circuit
Remarks * CMOS level output * CMOS level hysteresis input with standby control
digital output
F
digital output
digital input
STANDBY CONTROL
* CMOS level input without standby control G
digital input
* CMOS level hysteresis input without standby control
H
digital input
digital output
* CMOS level input * CMOS level hysteresis input without standby control
I
digital output
digital input
* CMOS level input
digital output
M
digital output
(Continued)
12
MB91307 Series
(Continued) Type
Circuit
Remarks * CMOS level input/output with standby control with pull-down resistance (25 k)
digital output
digital output
P
CONTROL
digital input
STANDBY CONTROL
Open drain control
* Open drain output CMOS level hysteresis input with standby control
Q
digital output
digital input
STANDBY CONTROL
13
MB91307 Series
HANDLING DEVICES
MB91307 Series * Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins (other than medium- and high-withstand voltage pins), or to voltages lower than VSS, as well as when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. When a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. * Treatment of unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. * About power supply pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 mF between VCC and VSS near this device. * Notes on Power-ON/shut-down Cautions to take when turning on/off VCCI (1.8-V internal power supply) and VSS (3.3-V external-pin power supply) Do not apply VSS (external) alone continuously (for over an indication of one minute) with VCCI (internal) disconnected not to cause a reliability problem with the LSI. When VSS (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for example, due to power supply noise. When the power is turned on VCCI (internal) VSS (external) Signal When the power is turned off * Precautions for use of stop mode The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when increased leak current (ICCH) in stop mode, or abnormal operation or power fluctuation due to noise while in operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that the external power supply does not fall below 3.3 V. And even if this should occur, the internal regulator can be set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to "L" level.) Signal VSS (external) VCCI (internal)
14
MB91307 Series
* Sample use of Stop Mode with 3.3 V power supply
3.3 V VCC 2.4 k C 7.6 k 0.1 F
VSS
GND
* About crystal oscillator circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. * Treatment of NC pins Any pins marked "NC" (not connected) must be left open. * About mode pins (MD0 to MD2) Mode pins (MD0 to MD2) should be connected directly to VCC or VSS . To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. * Operation at startup Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the "L" level input to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only the minimum setting for the stabilization wait period.) * Base oscillator input at startup At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended. * Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. * Precaution on using ports 6 and 7 If one of P60/A15 to P70/A24, which are shared for output of external bus interface addresses, is used as a port, a grid voltage is applied to the port instantaneously when the status of another address output pin is changed. Therefore, add resistors or capacitors to those ports to prevent application of the grid voltage.
15
MB91307 Series
* Clock control block For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time. * Bit search module The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible. * Prefetch When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits). Byte or halfword access results in wrong data read. * Setting of external bus The MB91307 series is guaranteed at an external bus frequency of 33 MHz. As the external bus is capable of supporting 66 MHz for future enhancements, the initial value is the same rate as the base clock (determined by the PLL setting) . The external bus is set to 66 MHz if you set the base clock to 66 MHz with the external-bus base clock division setting register (DIVR1) containing the initial value. To change the base clock frequency, set the external bus frequency not exceeding 33 MHz and set the new base clock frequency. * MCLK and SYSCLK MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either depending on each application. * I2C input/output pin The SDA and SCL pins of the MB91307 series are pseudo open-drain pins with the P-ch transistor turned off to prevent the "H" level from being output. As the circuit configuration has a diode added to the VCC side, therefore, the communication voltage must be adjusted to the 3.3-V power supply of this model (pulled up to a voltage of 3.3 V) . * Shared port function switching To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings. * Pull-up control Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the AC standard. Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby mode. * I/O port access Byte access only for access to port * Remarks for the external clock operation When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0 must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops when "H" is input in STOP mode. To prevent one output from competing against another, in this case, the stop mode must not be used. 16
MB91307 Series
X0
X1
MB91307 series
Using external clock (normal) Note : Stop mode (oscillation stop mode) cannot be used. * Low-power consumption modes * To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control register) and be sure to use the following sequence: (LDI #value_of_standby, R0) (LDI #_STCR, R12) STB R0, @R12 ; Write to standby control register (STCR) LDUB @R12, R0 ; Read STCR for synchronous standby LDUB @R12, R0 ; Read STCR again for dummy read NOP ; NOP x 5 for timing adjustment NOP NOP NOP NOP Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. * If you use the monitor debugger, follow the precautions below: Do not set a breakpoint within the above array of instructions. Do not single-step the above array of instructions. * Current at power-on (only for MB91V307R) About 300 mA of power supply current flows when the power is turned on with INIT set to 0. Set INIT to 1 to stop the overcurrent flowing. After that, the overcurrent will not flow even if INIT is set to 0. * Watchdog timer The watchdog timer function of this model monitors that a program delays a reset within a certain period of time and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes place. An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under a condition in which the CPU stops program execution. Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of control. If this is the case, use the external INIT pin to cause a reset (INIT).
17
MB91307 Series
* Terminal and timing control register (TCR) (0x00000683) The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit manipulation instruction. If you intend to disable sharing of the bus by writing "0" to Bit 7 (BREN bit) of TCR when the bit is "1", be sure to follow the procedure below. If the procedure is not followed, the device may hang up. 1. Write "0" to Bit 2 (BRQE bit) of the port 8 function register (PFR8). 2. Write "0" to Bit 7 (BREN bit) of TCR. * RD/WR CS hold extension cycle Assume that use of the RD/WR CS hold extension cycle is specified (Bit 0 of AWR is 1) for an area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are 0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and settings are specified in a specific combination. The hold extension cycle will not be inserted when the following conditions are met: * Use of the RD/WR CS hold extension cycle is specified. (Bit 0 [W00 bit] of AWR is 1.) * A normal memory/IO access type is set for the area. (Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.) Note: The MB91307 series allows only this type to be set. * Disuse of the address CS delay cycle is specified. (Bit 2 [W02 bit] of AWR is 0.) * A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle. (Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.) (Example: First word writing to an external bus 16-bit area) * If an access is made to write data larger than the bus width to the relevant area under the above conditions, the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of the data. Therefore, the hold time becomes insufficient. Note : This problem does not occur in the read cycle. To use this function, make either of the following settings: * Specify the use of the address CS delay cycle. (Set 1 for Bit 2 [W02 bit] of AWR.) * Specify 0 cycle for the write recovery cycle. (Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.) * Signed DIVIDE statement (DIVOS) When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access is done, a correct calculation result might not be obtained. This is generated under the following conditions. * When the instruction performs memory accesses just before a DIVOS instruction. Note : Instructions that performs relevant memory accesses (a total of 58 instructions) ST Ri, @- R15 STB Ri, @Rj STB Ri, @ (R14, disp8) LDUH @ (R13, Rj), Ri DMOVH @dir9, R13 18 ST Rs, @- R15 STB Ri, @ (R13, Rj) LDUB @Rj, Ri LDUB @ (R13, Rj), Ri DMOVB @dir8, R13 ST PS, @- R15 DMOVB R13, @dir8 LD @ (R13, Rj), Ri DMOV @dir10, R13 LD @ (R14, disp10), Ri
MB91307 Series
LDUH @ (R14, disp9), Ri ANDH Rj, @Ri EORB Rj, @Ri DMOVB @R13+, @dir8 DMOVB @dir8, @R13+ LDUB @ (R14, disp8), Ri ANDB Rj, @Ri DMOV @R13+, @dir10 DMOV @dir10, @R13+ DMOV @R15+, @dir10 AND Rj, @Ri ORB Rj, @Ri DMOVH @R13+, @dir9 DMOVH @dir9, @R13+ DMOV @dir10, @- R15
* When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned. * Even if the DIVOS and DIV1 instructions are 4-byte aligned, perform a D-bus DMA transfer or specify the full trace mode as trace mode if a breakpoint is set in the DIV1 instruction. Avoid this notes as follows: (1) Do not place an instruction that performs memory access before a DIVOS instruction. (2) Do not perform a DMA transfer to the D-bus or set full trace mode as trace made when a DIVOS instruction is specified. To output the code for avoiding above (1) condition, specify "-@div0s 1" as the compiler option. SOFTUNE compiler: * In case of using the SOFTUNE V3: after the SOFTUNE compiler V30L07R07 * In case of using the SOFTUNE V5: after the SOFTUNE compiler V50L04 * In case of using the SOFTUNE V6: after the SOFTUNE compiler V60L01 * DMA demand transfer In sleep mode, demand transfer is executed only once and processing does not go further. During normal operation, the efficiency of demand transfers may seem to be lowered. This action occurs only in demand transfers (it does not occur in DREQ edge detection mode or the like). This is occurred in the following cases: * A demand transfer by DMAC is performed in sleep mode. - After a demand transfer is performed once, processing does not go further although DREQ is input successively. - A subsequent transfer is started if the device is released from sleep mode and an external bus operation other than a DMA transfer occurs. * A demand transfer by DMAC is performed during normal operation. - After a demand transfer is performed once, a subsequent transfer is not performed until an external bus access other than a DMA transfer occurs. - A demand transfer does not progress while there is no external bus access because cache hitting is performed continuously or internal ROM operation continues. * A subsequent demand transfer is not started even if an external bus access for prefetching occurs. Avoid this notes as follows: * Do not perform a demand transfer by DMAC in sleep mode. * Do not use sleep mode during a demand transfer by DMAC.
19
MB91307 Series
* RMW instructions using R15 If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and, as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following instructions: AND OR EOR XCHB R15,@Rj R15,@Rj R15,@Rj @Rj,R15 ANDH ORH EORH R15,@Rj R15,@Rj R15,@Rj ANDB ORB EORB R15,@Rj R15,@Rj R15,@Rj
* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the state of the S flag of the PS register. Avoid this notes as follows: * When programming any of the above 10 instructions by an assembler, specify a general-purpose register in place of R15. * Executing instructions on RAM * If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8H to 0005 FFFFH. (Instruction code prohibited area) * Notes on the PS register Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. * The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu: (1) D0 and D1 flags are updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as those in (1) above. * The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger event has occurred. (1) The PS register is updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as that in (1) above. * Notes on I-bus Memory Do not access data in the instruction cache control register or the instruction cache RAM immediately before the RETI instruction.
20
MB91307 Series
Unique to the evaluation chip MB91V307R * Simultaneous occurrences of a software break and a user interrupt/NMI When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause the following phenomena: * The debugger stops pointing to a location other than the programmed breakpoints. * The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. * Single-stepping the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. * Break function * If the address of a current system stack pointer or an area that includes a stack pointer is specified as an object address of a hardware break (including an event break), a break occurs after one instruction is executed. The break occurs although the relevant user program does not include an actual data access instruction. To avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer as a target of a hardware break (including an event break). * If an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. Example: LD LD CALL @R1,R0 ; read F-bus RAM @R2,R3 ; read F-bus RAM @R0 ; An incorrect alignment error may occur or a break might not occur.
To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger function setup. To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software break in debugger function setup. * Trace mode If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer, the current may increase or DMA access to the D-bus may be lost. This is occurred if: * A DMA transfer to the D-bus or standby mode occurs in full trace mode. Use internal trace mode to avoid this notes.
21
MB91307 Series
* Alignment error (emulator debugger) Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction. Under these conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown break factor or a CPU error break is output. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. This problem occurs if the following three types of instructions are executed successively: (1) LD or DMOV instructions causing a wait (reading a branch destination address) LD @Rj,Ri LDUH @Rj,RI LD @(R13,Rj)Ri LDUH @(R13,Rj),Ri LDUB @(R13,Rj),Ri LD @(R14,disp10),Ri LDUH @(R14,disp9),Ri LDUB @(R14,disp8),Ri LD @R15+,Ri LD @R15+,Rs LD @R15+,PS DMOV @dir10,R13 DMOVH @dir9,R13 DMOVB @dir8,R13 (2) Instructions causing a wait (reading F-bus RAM or external memory) (3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D Example: LD@R1,R0 ;read F-bus RAM LD@R2,R3 ;read F-bus RAM CALL @R0 Avoid this notes as follows: Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction. Under these conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown break factor or a CPU error break is output. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. Avoid this problem as follows: * To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger function setup. * To perform the instruction break correctly, set the break point in an address other than the branch destination address. * Operand break A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer.
22
MB91307 Series
BLOCK DIAGRAM
CPU Core
32 32
Bit search
Instruction cache 1K bytes
RAM*
Bus Converter
DMAC 5 channels
32 32 16 Adapter 16
Clock control External memory interface
UART 3 channels
U-TIMER 3 channels
I2C 1 channel
Interrupt controller
External interrupt
Reload timer 3 channels
A/D 4 channels
Port
* : Internal RAM 128K bytes for MB91307R 64K bytes for MB91306R
23
MB91307 Series
CPU AND CONTROL BLOCK
Internal Architecture The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set intended for built-in applications.
1. Features
* Uses of RISC Architecture Basic instruction set: 1 instruction to 1 cycle. * 32-bit architecture General-purpose registers: 32-bits x 16 registers * 4G bytes linear memory space * Built-in multipliers 32-bit x 32-bit multiplication: 5 cycles 16-bit x 16-bit multiplication: 3 cycles * Enhanced interrupt processing High-speed response (6 cycles) Multiple interrupt support Level masking functions (16 levels) * Enhanced I/O operating instructions Memory-to-memory transfer instructions Bit processing instructions * High code efficiency Basic instruction length: 16 bits * Low power consumption Sleep mode, stop mode * Gear function
24
MB91307 Series
2. Internal Architecture
The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction bus (I-bus) is connected to an on-chip instruction cache. a 32-bit 16-bit bus converter is connected to the bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard Princeton bus converter is connected to the both the I-bus and D-bus as an interface between the CPU and bus controller.
FRex CPU D-bus I-bus
I address Instruction cache
32
I data
32
Harvard
D address
32 Princeton bus converter
D data
32
F address RAM
32
F data
32
32 bit
16 bit Bus converter
16 R-bus X-bus
Peripherals resource
Bus controller
25
MB91307 Series
3. Programming Model
* Basic Programming Model
32 bits [Default values]
R0
XXXX XXXXH
R1
General-purpose register
R12 R13 AC
R14
FP
XXXX XXXXH 0000 0000H
R15
SP
Program counter Program status
PC
PS
ILM
SCR
CCR
Table base register
TBR
Return pointer
RP
System stack pointer User stack pointer
SSP
USP
Multiplier result registers
MDH MDL
26
MB91307 Series
4. Registers
* General Purpose Register 32 bits [Default values]
R0 R1
XXXX XXXXH
R12 R13 R14 R15
AC FP SP XXXX XXXXH 0000 0000H
Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for computation operations, or as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13: Virtual accumulator R14: Frame pointer R15: Stack pointer Default values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). * PS (Program Status Register) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All bits not defined in the diagram are reserved bits with read value "0" at all times. Write access to these bits is not enabled. Bit position 31
20 16 10 87 0
ILM
SCR
CCR
PS Register * CCR (Condition Code Register)
7 6 5 S 4 I 3 N 2 Z 1 V 0 C
[Default value] - - 00XXXXB
S I N Z V C
CCR Register : Stack flag, cleared to "0" at reset. : Interrupt flag, cleared to "0" at reset. : Negative flag, default value at reset undefined. : Zero flag, default value at reset undefined. : Overflow flag, default value at reset undefined. : Carry flag, default value at reset undefined. 27
MB91307 Series
* SCR (System Condition code Register)
10 D1 9 D0 8 T
[Default value] XX0B
SCR Register Stepwise division flags These flags store interim data during execution of stepwise division. Step trace trap flag Indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. * ILM(Interrupt Level Mask Register)
20 19 18 17 16
[Default value] 01111B
ILM4 ILM3 ILM2 ILM1 ILM0
ILM Register This register stores interrupt level mask values, for use in level masking. The register is initialized to value 15 (01111B) at reset. * PC (Program Counte Registerr)
31 PC 0
[Default value] XXXXXXXXH
PC Register The program counter indicates the address of the instruction that is executing. The default value at reset is undefined. * TBR (Table Base Register)
31 TBR 0
[Default value] 000FFC00H
TBR Register The table base register stores the starting address of the vector table used in EIT processing. The default value at reset is 000FFC00H.
28
MB91307 Series
* RP (Return Pointer)
31 RP 0
[Default value] XXXXXXXXH
RP Register The return register stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to this PC register. The default value at reset is undefined. * SSP (System Stack Pointer)
31 SSP 0
[Default value] 00000000H
SSP Register The SSP register is the system stack pointer. When the S flag is "0," this register functions as the R15 register. The SSP register can also be explicitly specified. This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an EIT occurs. The default value at reset is 00000000H. * USP (User Stack Pointer)
31 USP 0
[Default value] XXXXXXXXH
USP Register The USP register is the user stack pointer. When the S flag is "1," this register functions as the R15 register. The USP register can also be explicitly specified. The default value at reset is undefined. This register cannot be used with RETI instructions. * Multiply & Divide registers
31 MDH MDL 0
Multiply & Divide Registers The multiply and divide registers are each 32 bits in length. The default value at reset is undefined. 29
MB91307 Series
SETTING MODE
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode.
1. Mode Pins
The three pins MD2, MD1, MD0 are used in mode vector fetch instructions, and also to make settings in test mode. Mode pin Mode name Reset vector access area Remarks MD2 MD1 MD0 0 0 1 External ROM mode vector Outside Bus width is set by mode register.
2. Mode Register (MODR)
The mode data fetch instruction writes data to the address "0000 07FDH" called the mode data. The area "0000 07FDH" is the mode register (MODR). When a setting is made to this register, the device will operate the mode corresponding to that setting. The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register from a user program. Note : No data exists at the FR family mode register address (0000 07FFH).
< Detailed register description >
MODR Address 0000 07FDH
7 0 6 0 5 0 4 0 3 0 2 ROMA 1 WTH1 0 WTH0
Default XXXXXXXXB
Operating mode setting bits
[bit7 to bit3] Reserved bits These bits should always be set to "00000." If set to any other value, stable operation is not assured. [bit2] ROMA (Internal RAM enable bit) This bit indicates whether internal RAM is enabled. ROMA Function 0 1 External ROM mode Internal RAM mode Remarks The built-in RAM area functions as external area. The built-in RAM area is enabled. The 128K bytes built-in RAM can be used.
[bit1, 0] WTH1, WTH0 (Bus width indicator bits) In external bus mode, these bits determine the bus width setting. In external bus mode, the value of these bits sets the BW1, 0 bits in the AMD0 register (CS0 area). WTH1 WTH0 Bus width 0 0 1 1 30 0 1 0 1 8-bit 16-bit Setting prohibited Setting prohibited
MB91307 Series
MEMORY SPACE
1. Memory Space
The FR family has 4G bytes (232 addresses) of logical address space with linear access from the CPU. *Direct Addressing Areas The following areas of address space are used for I/O operations. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct areas differ according to the size of the data accessed, as follows. byte data access : 000H to 0FFH half word data access : 000H to 1FFH word data access : 000H to 3FFH
2. Memory Map
The following diagram illustrates memory space in the FR family.
MB91307R Internal ROM external bus mode MB91306R Internal ROM external bus mode MB91306R/MB91307R External bus mode
0000 0000H I/O 0000 0400H I/O 0001 0000H
Access prohibited Access prohibited Internal RAM 128K bytes External area Access prohibited Access prohibited Access prohibited
0000 0000H I/O I/O 0000 0400H I/O I/O 0001 0000H
Direct addressing area Refer to I/O map
0004 0000H 0005 0000H 0006 0000H
Internal RAM 128K bytes
0004 0000H
0006 0000H
0010 0000H
0010 0000H
External area
External area
External area
FFFF FFFFH
31
MB91307 Series
*Use of Built-in RAM The MB91307R contains 128K bytes of internal RAM, and MB91306R contains 64K bytes of internal RAM. To enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1). Precautions for use of this model * The reset vector is fixed at 000F FFFCH. * For the MB91307R, the 128K bytes RAM area is from 0004 0000H to 0005 FFFFH and for the MB91306R, the 64K bytes RAM area is from 0004 0000H to 0004 FFFFH. The area from 0006 0000H to 000F FFFFH is access prohibited. * In order to use RAM the mode register must be set to internal ROM external bus mode. * In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F FFXXH is an internal area and cannot be accessed externally. Please refer to the following explanation. * When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005 FFF8H to 0005 FFFFH. (This is an instruction code prohibited area.)
After reset release
After mode setting Internal ROM external bus mode
0000 0000H I/O 0000 0400H I/O 0001 0000H
Access prohibited
Direct addressing area
I/O
I/O
Refer to I/O map
I/O
I/O
Access prohibited
Access prohibited Internal RAM 64K bytes
0004 0000H 0005 0000H 0006 0000H
External area Access prohibited External area Internal RAM 128K bytes
Access prohibited
0010 0000H
External area
External area
External area
FFFF FFFFH
: The shaded portion is an internal area. After mode register setting the vector area is an internal area. Therefore before writing to the mode register it is necessary to rewrite the TBR register so that the vector area is changed to an external area.
32
MB91307 Series
USER PROGRAM INITIALIZATION
The following sequence describes an example using built-in RAM. For the MB91306R, only the internal RAM area is different but the setting is same.
1. Hardware Setting Conditions
MB91307 series
CS0
External ROM
A19 to A1
1) Assume that 1M bytes of external ROM is placed beginning at 0010 0000H. Place the program at this location in the linker. (The following description can apply to other addresses than this one as well.) 2) Connect addresses A19 to A1 (1M bytes) to ROM, other addresses will use CS0. 3) Set the mode pins (MD2, MD1, MD0) to external vectors. 4) Write the reset vector to 001F FFFCH. Likewise write the mode vector to 001F FFF8H.
2. Immediately After Reset Release
0000 0000H
MB91307 series
CS0
External ROM
0004 0000H External ROM
FFFF FFFFH
1M bytes of ROM can be viewed again on the address map.
1)
After reset release, the CPU will attempt to load a mode vector from 000F FFF8H, a reset vector from 000F FFFCH, however because this will be an external vector, the CPU will have to go externally. However the CS0 default value causes 1M bytes of external ROM to be repeated in external space, so that the mode vector and the reset vector itself will load the contents written at 001F FFF8H and 001F FFFCH in external ROM. 2) The branch destination is set in the linker to an address in the area 001X XXXXH, so that subsequent program execution will be in this area.
33
MB91307 Series
3. User Program Initialization Steps
0000 0000H
MB91307 series
CS0
External ROM
0004 0000H
0010 0000H External ROM 001F FFFFH FFFF FFFFH
1M bytes of ROM space matches 1M bytes of the address map.
1) Set the TBR register so that the interrupt table is 001F FFXXH, then perform initialization. This process also includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X XXXXH. The CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs on external ROM. 2) If necessary, initialize the contents of RAM. 3) Now initialization is complete, and the application program can be executed.
34
MB91307 Series
I/O MAP
This map shows the correlation between areas of memory space and individual registers in peripheral resources. [How to read the map] Address 000000H Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port Data Register
Read/write attributes Register default value after reset Register name (1-column registers at address 4n, 2-column registers at address 4n + 2...) Left most register address (for word access, the first column of the register contains the MSB end of the data)
Note: Default register bit values are indicated as follows: "1" : Default value "1" "0" : Default value "0" "X" : Default value "X" "-" : No physical register at this location
35
MB91307 Series
Register +0 PDR8 [R/W] --X--XXX +1 PDR9 [R/W] XXXXXXX PDRG [R/W] -----XXX PDRH [R/W] XXX00XXX PDRI [R/W] ---XXXXX PDRJ [R/W] XXXXXXXX R-bus Port Data Register +2 PDR2 [R/W] XXXXXXXX PDR6 [R/W] XXXXXXXX PDRA [R/W] XXXXXXXX +3 PDR7 [R/W] -------X PDRB [R/W] XXXXXXXX T-unit Port Data Register
Address 000000H 000004H 000008H 00000CH 000010H 000018H to 00001CH 000020H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H
Block
EIRR [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R/W] 0--11111 ELVR [R/W] 00000000 TMR [R] XXXXXXXX XXXXXXXX TMCSR [R/W] ----0000 00000000 TMR [R] XXXXXXXX XXXXXXXX TMCSR [R/W] ----0000 00000000 TMR [R] XXXXXXXX XXXXXXXX TMCSR [R/W] ----0000 00000000 SIDR [R/W] XXXXXXXX SCR [R/W] 00000100 DRCL [W] -------SCR [R/W] 00000100 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0-
Reserved
Ext int DLYI/I-unit
TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX SSR [R/W] 00001-00
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0 U-TIMER 0 UART1 (Continued)
UTIM [R] (UTIMR [W] ) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
36
MB91307 Series
Address 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H
Register +0 +1 +2 DRCL [W] -------SCR [R/W] 00000100 DRCL [W] -------ADCS +3 UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 [R/W] UTIM [R] (UTIMR [W] ) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
Block U-TIMER 1 UART2 U-TIMER 2 A/D Converter sequential comparator Reserved Reserved Reserved Reserved Reserved Reserved
UTIM [R] (UTIMR [W] ) 00000000 00000000 ADCR [R] ------XX XXXXXXXX IBCR [R/W] 00000000 IBSR [R/W] 00000000
00000000 00000000
ITBA [R/W] ------00 00000000 ISMK [R/W] 01111111 ICCR [R/W] 0-011111 ISBA [R/W] 00000000 IDBL [R/W] -------0 Reserved Reserved Reserved Reserved Reserved (Continued) 37 I2C interface
ITMK [R/W] 00----11 11111111 IDAR [R/W] 00000000
MB91307 Series
Address 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 000274H 000278H 00027CH 000280H to 0002FCH
Register +0 +1 DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX +2 +3
Block
DMAC
Reserved
DMAC
Reserved
Reserved Reserved
Reserved (Continued)
38
MB91307 Series
Register +0 +1 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG [R/W] ----000 DDRH [R/W] 00011000 PFRG [R/W] ----0000 PFRH [R/W] 0000000 PFRI [R/W] --00-00 DDRI [R/W] --000000 DDRJ [R/W] 00000000 R-bus Port Direction Register Bit Search Module ICHRC [R/W] 0 - 000000 ISIZE [R/W] ------00 +2 +3
Address 000300H 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H to 00043CH
Block Reserved Instruction Cache
Reserved
Instruction Cache
Reserved
R-bus Port Function Register
Reserved (Continued) 39
MB91307 Series
Register +0 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 +1 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 RSRR [R/W] 10000000 *
2
Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H
+2 ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111
+3 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111
Block
Interrupt Control unit
Interrupt Control unit
TBCR [R/W] CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 *1 Reserved Clock Control unit
STCR [R/W] 00110011 * WPR [W] XXXXXXXX
2
00XXXX00 *
1
CLKR [R/W] 000484H 00000000 * 000488H to 0005FCH
1
DIVR0 [R/W] 00000011 *1
*1: These registers have different default values at reset level. The value shown is the INIT level value. *2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT pin. (Continued) 40
MB91307 Series
Address 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H to 00063FH 000640H 000644H 000648H 00064CH 000650H 000654H
Register +0 DDR8 [R/W] --0--000 +1 DDR9 [R/W] 00000000 PFR8 [R/W] --1--0-PFRB2 [R/W] 00----- ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ASR4 [R/W] XXXXXXXX XXXXXXXX ASR5 [R/W] XXXXXXXX XXXXXXXX ACR0 [R/W] 1111XX00 00000000 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX PFR9 [R/W] 1111111 PFR6 [R/W] 11111111 PFRA [R/W] 0-001101 PFR7 [R/W] -------1 PFRB1 [R/W] 00000000 +2 DDR2 [R/W] 00000000 DDR6 [R/W] 00000000 DDRA [R/W] 00000000 +3 DDR7 [R/W] 00000000 DDRB [R/W] 00000000
Block
T-unit Port Direction Register
T-unit Port Function Register
Reserved
T-unit
(Continued)
41
MB91307 Series
Address 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000684H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H
Register +0 ASR6 [R/W] XXXXXXXX XXXXXXXX ASR7 [R/W] XXXXXXXX XXXXXXXX AWR0 [R/W] 011111111 11111111 AWR2 [R/W] XXXXXXXX XXXXXXXX AWR4 [R/W] XXXXXXXX XXXXXXXX AWR6 [R/W] XXXXXXXX XXXXXXXX IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W] XXXXXXXX XXXXXXXX CSER [R/W] 000000001 CHER [R/W] 11111111 ESTS0 [R/W] ESTS1 [R/W] X0000000 0X000000 XXXXXXXX 00000000 ECTL0 [R/W] ECTL1 [R/W] ESTS2 [R] 1XXXXXXX ECTL2 [W] 000X0000 ECTL3 [R/W] 00X00X11 TCR [R/W] 00000000 XXXXXXXX +1 +2 ACR6 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX AWR1 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX +3
Block
T-unit
Reserved Reserved
DSU
(Continued)
42
MB91307 Series
Address 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H
Register +0 ECNT0 [W] XXXXXXXX +1 ECNT1 [W] XXXXXXXX +2 EUSA [W] XXX00000 EDTR1 [W] XXXXXXXX XXXXXXXX EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX +3 EDTC [W] 0000XXXX
Block
EWPT [R] 00000000 00000000 EDTR0 [W] XXXXXXXX XXXXXXXX
DSU
(Continued) 43
MB91307 Series
(Continued) Address 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H Register +0 +1 EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMAC DMAC Reserved DSU +2 +3 Block
44
MB91307 Series
INTERRUPT SOURCES AND INTERRUPT VECTORS
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI requ External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0(RX completed) UART1(RX completed) UART2(RX completed) UART0(TX completed) UART1(TX completed) UART2(TX completed) DMAC0(end, error) Interrupt number Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 Interrupt level 15 (FH) ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 Offset TBR default address 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H (Continued) 45
MB91307 Series
Interrupt source DMAC1(end, error) DMAC2(end, error) DMAC3(end, error) DMAC4(end, error) A/D I2C System reserved System reserved System reserved System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Delay interrupt source bit System reserved (REALOS use) System reserved (REALOS use) System reserved System reserved System reserved 46
Interrupt number Decimal 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Hex 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44
Interrupt level ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset TBR default address 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH (Continued)
MB91307 Series
(Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instructions Interrupt number Decimal 69 70 71 72 73 74 75 76 77 78 79 80 to 255 Hex 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset TBR default address 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
47
MB91307 Series
PERIPHERAL RESOURCES
1. Interrupt Controller
(1) Overview The interrupt controller receives and processes arbitration of interrupts. *Hardware Configuration This module is configured from the following elements. * ICR register * Interrupt priority determination circuit * Interrupt level and interrupt number (vector) generator * Hold request removal request generator *Principal Functions This module primarily provides the following functions. * NMI request / interrupt request detection * Order of priority determination (according to level and number) * Notification (to CPU) of interrupt level of source according to determination * Notification (to CPU) of interrupt number of source according to determination * Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level "11111" is generated * Generation of hold request removal requests to the bus master
48
MB91307 Series
(2) Register List
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 R 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000440H Address : 00000441H Address : 00000442H Address : 00000443H Address : 00000444H Address : 00000445H Address : 00000446H Address : 00000447H Address : 00000448H Address : 00000449H Address : 0000044AH Address : 0000044BH Address : 0000044CH Address : 0000044DH Address : 0000044EH Address : 0000044FH Address : 00000450H Address : 00000451H Address : 00000452H Address : 00000453H Address : 00000454H Address : 00000455H Address : 00000456H Address : 00000457H Address : 00000458H Address : 00000459H Address : 0000045AH Address : 0000045BH Address : 0000045CH Address : 0000045DH Address : 0000045EH Address : 0000045FH

ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
(Continued) 49
MB91307 Series
(Continued)
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 R 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000460H Address : 00000461H Address : 00000462H Address : 00000463H Address : 00000464H Address : 00000465H Address : 00000466H Address : 00000467H Address : 00000468H Address : 00000469H Address : 0000046AH Address : 0000046BH Address : 0000046CH Address : 0000046DH Address : 0000046EH Address : 0000046FH

ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Address : 00000045H
MHALTI R/W
LVL4 R
LVL3 R/W
LVL2 R/W
LVL1 R/W
LVL0 R/W
HRCL
50
MB91307 Series
(3) Block Diagram
UNMI
WAKEUP ("1" when LEVEL 11111)
Determine order of priority
5
NMI processing HLDREQ hold request
LEVEL4 to LEVEL0
MHALTI
LEVEL determination
RI00
ICR00
VECTOR determination
LEVEL, VECTOR generation
6
VCT5 to VCT0
RI47 (DLYIRQ)
ICR47
R-bus
51
MB91307 Series
2. External Interrupt - NMI Control Block
(1) Overview The External Interrupt-control block controls external interrupt requests input at the NMI and INT0 to INT7 pins. The request level can be selected from "H," "L," "rising edge," or "falling edge" detection (except for NMI). (2) Register List
* External interrupt enable register (ENIR)
bit
7 EN7
6 EN6
5 EN5
4 EN4
3 EN3
2 EN2
1 EN1
0 EN0
* External interrupt source register (EIRR)
bit
15 ER7
14 ER6
13 ER5
12 ER4
11 ER3
10 ER2
9 ER1
8 ER0
* Request level setting register (ELVR)
bit
15 LB7
14 LA7 6 LA3
13 LB6 5 LB2
12 LA6 4 LA2
11 LB5 3 LB1
10 LA5 2 LA1
9 LB4 1 LB0
8 LA4 0 LA0
bit
7 LB3
(3) Block Diagram
R-bus 8
Interrupt enable register
Interrupt request
9
Gate
Source F/F
Edge detection circuit
9
INT0 to INT7 NMI
8
Interrupt source register
8
Interrupt level setting register
52
MB91307 Series
3. REALOS Related Hardware
REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these resources cannot be used by user programs. * Delay Interrupt Module (1) Overview The delay interrupt module is a module that generates interrupts for task switching. This module can be used with software instructions to generate and cancel interrupts to the CPU. (2) Register List
bit
Address :
7
6
5
4
3
2
1
0 DLYI [R/W]
00000044H
DICR
(3) Block Diagram
R-bus
Interrupt request
DLYI
53
MB91307 Series
* Bit Search Module (1) Overview Searches data written to input registers for "0" or "1" or change points, and outputs the value of the detected bits. (2) Register List
31
Address : Address : Address : Address :
0 BSD0 BSD1 BSDC BSRR
000003F0H 000003F4H 000003F8H 000003FCH
0 detection data register 1 detection data register Change point detection register Detection results register
(3) Block Diagram
D-bus
Input latch
Address decoder
Detection mode
1 detection data capture
Bit search circuit
Search results
54
MB91307 Series
4. 16-bit Reload Timer
(1) Overview The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock generation, and a control register. For the input clock signal, a selection of three internal clock signals (machine clock multiplied by 2, 8, or 32) or external clock is provided. The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square wave indicating counting in progress in one-shot mode. The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in internal clock mode. The external event count function can be used in reload mode or as a frequency multiplier in external clock mode. The MB91306R/MB91307R contain 3 channels (0 to 2) of this timer. (2) Register List
* Control status register (TMCSR)
15 7 MOD0 14 6 13 5 OUTL 12 4 RELD 11 CSL1 3 INTE 10 CSL0 2 UF 9 MOD2 1 CNTE 8 MOD1 0 TRG
* 16-bit timer register (TMR)
15 0
* 16-bit reload register (TMRLR)
15 0
55
MB91307 Series
(3) Block Diagram
16
16-bit reload register
R-bus
8
Reload
RELD
16-bit down counter
OUTE OUTL
16 2 GATE CSL1
Clock selector
OUT CTL. 2
INTE UF CNTE IRQ
CSL0
Re-trigger
TRG
Port (TIN) Port (TOT)
2 IN CTL. EXCK
Prescaler clear
3 MOD2 MOD1
21 23 25
Internal clock
MOD0
3
56
MB91307 Series
5. U-TIMER (16 bit timer for UART baud rate generation)
(1) Overview The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of chip operating frequency and U-TIMER reload value. The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event. This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers in a cascade connection, it is possible to count intervals up to a maximum of 232 x . The available case connections are channel 0 to channel 1, and channel 1 to channel 2. (2) Register List
15
87 UTIM UTIMR UTIMC
0 (R) (W) (R/W)
(3) Block Diagram
15 UTIMR (reload register) Load 15 UTIM (timer) Clock Underflow
(Peripheral clock) MUX Channel 0 only
0
0
control
f.f.
To UART
Under flow U-TIMER 1
57
MB91307 Series
6. UART
(1) Overview The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing the following features. This device features a 3-channel built-in UART. * * * * * * * * * Full duplex double buffer Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled Supports multi-processor mode Fully programmable baud rate Built-in timer can be set to any desired baud rate (see U-TIMER description) Independent baud rate setting from external clock enabled. Error detection functions (parity, framing, overrun) Transfer signal NRZ encoded DMA transfer start from interrupt enabled DMAC interrupt source cleared by write operation to DRCL register.
(2) Register List
15 SCR SSR 87 SMR SIDR (R)/SODR (W) 0 (R/W) (R/W)
DRCL 8 bit 8 bit
(W)
* Serial input register/Serial output registe (SIDR/SODR)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
* Serial status register (SSR)
7 PE 6 ORE 5 FRE 4 RDRF 3 TDRE 2 1 RIE 0 TIE
* Serial mode register (SMR)
7 MD1 6 MD0 5 4 3 CS0 2 1 SCKE 0
* Serial control register (SCR)
7 PEN 6 P 5 SBL 4 CL 3 A/D 2 REC 1 RXE 0 TXE
* DRCL register (DRCL)
7 6 5 4 3 2 1 0
58
MB91307 Series
(3) Block Diagram
Control signal RX interrupt (to CPU) SC (clock) From U-TIMER Clock select circuit External clock SC RX control circuit SI (receiving data) Start bit detect circuit Receiving bit counter Receiving parity counter TX control circuit Sent start circuit Sending bit counter Sending parity counter SO (Sending data) RX clock TX clock TX interrupt (to CPU)
Receiving status decision circuit
Receiving shifter
Sending shifter Sending start
Receiving end
SIDR
DMA receiving error signal (to DMAC)
SODR
R-bus
MD1 MD0
SMR register SCR register
CS0 SCKE SOE
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signal
59
MB91307 Series
7. A/D Converter (Sequential comparison type)
(1) Overview This A/D converter is a module that coverts analog input voltages to digital values, and provides the following features. Minimum conversion time 5.4 s/ch (at machine clock 33 MHz-CKLP) Built-in sample & hold circuit Resolution 10 bits (8-bit accuracy) Analog input: 4 channels by program selection Single conversion mode: Conversion on 1 select channel Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program. Continuous conversion mode: Continuous conversion on selected channel Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied (enables synchronized conversion start) * DMA transfer start from interrupt enabled * Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge). * * * *
(2) Register List
* Control status register (ADCS)
bit
15 BUSY
14 INT 6 MD0
13 INTE 5 ANS2
12 PAUS 4 ANS1
11 STS1 3 ANS0
10 STS0 2 ANE2
9 STRT 1 ANE1
8 0 ANE0
bit
7 MD1
* Data register (ADCR)
bit
15
14 6 6
13 5 5
12 4 4
11 3 3
10 2 2
9 9 1 1
8 8 0 0
bit
7 7
60
MB91307 Series
(3) Block Diagram
AVCC
AVRH AVSS
Internal voltage
Sample & hold circuit
Input switch
Sequential
Data register (ADCR)
Channel decoder Timing generator
AD control register
Clock (CLKP)
Prescaler ATG (External pin trigger)
Reload timer ch1 (Internal connection)
(4) Precautions for Use: When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source bits STS1, STS0 are set, and at this time the input values for the external trigger and internal timer should be set to the inactive side. If these values are set to the active side, abnormal operation may result. When setting the STS1, STS0 bits, set ATG = "1" input, reload timer (channel 2) = "0" output. Note : If internal impedance is higher than the specified value, it may not be possible to obtain analog input value sampling within the specified sampling time, so that proper results will not be obtained.
R-bus
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MB91307 Series
8. I2C Interface
(1) Overview The I2C interface operates as a master/slave device on the I2C bus at serial I/O ports with IC bus support. The following features are provided. * Master/slave sending and receiving * Arbitration function * Clock synchronization function * Slave address/general call address detection function * Transfer direction detection function * Start condition repeat generation and detection function * Bus error detection function * 10-bit/7-bit master/slave addressing * Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps) * Transfer end interrupt/bus error interrupt generation
(2) Register List * Bus Control Register (IBCR)
15 14 BEIE R/W 0 13 SCC R/W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0
Address : 000094H Default value * Bus Status Register (IBSR)
BER R/W 0
7
6 RSC R 0
5 AL R 0
4 LRB R 0
3 TRX R 0
2 AAS R 0
1 GCA R 0
0 ADT R 0
Address : 000095H Default value * 10-Bit Slave Address Register
BB R 0
15
14 6 TA6 R/W 0
13 5 TA5 R/W 0
12 4 TA4 R/W 0
11 3 TA3 R/W 0
10 2 TA2 R/W 0
9 TA9 R/W 0
8 TA8 R/W 0
Address : 000096H Default value
7
1 TA1 R/W 0
0 TA0 R/W 0
Address : 000097H Default value
TA7 R/W 0
(Continued)
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MB91307 Series
(Continued)
* 10-Bit Slave Address Mask Register (ITMK)
15 14 RAL R 0 13 5 TM5 R/W 1 12 4 TM4 R/W 1 11 3 TM3 R/W 1 10 2 TM2 R/W 1 9 TM9 R/W 1 8 TM8 R/W 1
Address : 000098H Default value
ENTB R/W 0
7
6 TM6 R/W 1
1 TM1 R/W 1
0 TM0 R/W 1
Address : 000099H Default value
* 7-Bit Slave Address Register (ISBA)
TM7 R/W 1
7
6 SA6 R/W 0
5 SA5 R/W 0
4 SA4 R/W 0
3 SA3 R/W 0
2 SA2 R/W 0
1 SA1 R/W 0
0 SA0 R/W 0
Address : 00009BH Default value

* 7-Bit Slave Address Mask Register (ISMK)
15 14 SM6 R/W 1 13 SM5 R/W 1 12 SM4 R/W 1 11 SM3 R/W 1 10 SM2 R/W 1 9 SM1 R/W 1 8 SM0 R/W 1
Address : 00009AH Default value
* Data Register (IDAR)
ENSB R/W 0
7
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
Address : 00009DH Default value
* Clock Control Register (ICCR)
D7 R/W 0
15
14
13 EN R/W 0
12 CS4 R/W 1
11 CS3 R/W 1
10 CS2 R/W 1
9 CS1 R/W 1
8 CS0 R/W 1
Address : 00009EH Default value
* Clock Disable Register (IDBL)
TEST W 0
7
6
5
4
3
2
1
0 DBL R/W 0
Address : 00009FH Default value

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MB91307 Series
(3) Block Diagram
ICCR EN IDBL DBL R-bus ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB
Repeat start Clock multiplier 2 Clock enabled I2 C operation enabled
2345
32
Sync
Shift clock generator
Clock select 2 (1/12) Shift clock edge change Bus busy
RSC LRB TRX ADT AL IBCR BER BEIE Last Bit
TX/RX
Start - stop condition detector Error
First Byte
Arbitration lost detector
SCL
Interrupt request
IRQ
SDA
INTE INT IBCR
Start End Master
SCC MSS
ACK OK Start - stop condition generator
ACK
GC-ACK OK
GCAA
IDAR IBSR AAS GCA ENTB ISMK RAL ITBA ITMK ISBA ISMK
Slave Global call Slave address compare
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MB91307 Series
9. DMAC (DMA Controller)
(1) Overview This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices. DMA transfer controlled by this module increases system performance by enabling high speed transfer of many types of data without going through the CPU. *Hardware Configuration This module is principally configured from the following units: * Five independent DMA channels * 5 channels independent access control circuit * 32-bit address registers (reload enabled: 2 per channel) * 16-bit transfer count registers (reload enabled: 2 per channel) * 4-bit block count registers (1 per channel) * External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0, ch1, ch2 only) * External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0, ch1, ch2 only) * DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0, ch1, ch2 only) * Fly-by transfer (memory to I/O, memory to memory) (ch0, ch1, ch2 only) * Two-cycle transfer *Principal Functions Data transfer using the DMAC module primarily involves the following functions: * Supports independent data transfer on multiple channels (5 channels) (1) Order of priority (ch0 > ch1 > ch2 > ch3 > ch4) (2) The order can be reversed between ch0 and ch1. (3) DMAC startup sources * Input from an external-only pin (edge detection/level detection, ch0, ch1, ch2 only) * Request from a built-in peripheral (shared interrupt request, including external interrupts) * Software request (register write) (4) Transfer modes * Demand transfer / burst transfer / step transfer / block transfer * Addressing mode 32-bit full address designation (increment/decrement/fixed) (address increment can be specified up to -255 to +255) * Data type, byte / half-word / word length * Single-shot / reload selection available
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MB91307 Series
(2) Register Descriptions
(bit)
31
24
23
16
15
08
07
00
ch0 Control/status register A ch0 Control/status register B ch1 Control/status register A ch1 Control/status register B ch2 Control/status register A ch2 Control/status register B ch3 Control/status register A ch3 Control/status register B ch4 Control/status register A ch4 Control/status register B Overall control register ch0 Transfer source address register ch0 Transfer source address register ch1 Transfer source address register ch1 Transfer source address register ch2 Transfer source address register ch2 Transfer source address register ch3 Transfer source address register ch3 Transfer source address register ch4 Transfer source address register ch4 Transfer source address register
DMACA0 0000200H DMACB0 0000204H DMACA1 0000208H DMACB1 000020CH DMACA2 0000210H DMACB2 0000214H DMACA3 0000218H DMACB3 000021CH DMACA4 0000220H DMACB4 0000224H D M A C R 0000240H
DMASA0 0001000H DMADA0 0001004H DMASA1 0001008H DMADA1 000100CH DMASA2 0001010H DMADA2 0001014H DMASA3 0001018H DMADA3 000101CH DMASA4 0001020H DMADA4 0001024H
66
MB91307 Series
(3) Block Diagram
Counter DMA transfer request to bus controller Buffer Selector
Write back
DMA start source selection circuit & request acceptance control
Peripheral start request/stop input External pin start request/stop input
DTC two-stage register DTCR Counter
DSS3 to DSS0
Buffer
Priority circuit
To interrupt controller
Read Write
Read/write control
Selector
IRQ4 to IRQ0 MCLREQ
ERIR, EDIR
Status transition circuit Peripheral interrupt clear
TYPE, MOD, WS
BLK register
Bus control block
Selector
DDNO
DDNO register
To bus controller
DMA controller Counter/buffer Selector
DDAD two-stage register
SDAM, SASZ7 to SASZ0 SADR
Address counter
Access address
Write back
Counter/buffer
Selector
DDAD two-stage register
DADM, DASZ7 to DASZ0 DADR
Write back
DMAC 5-channel Block Diagram
Bus control block
X-bus
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MB91307 Series
10. External Interface
(1) Overview The external interface controller controls the interface between the LSI's internal bus and external memory or I/ O devices. This section describes the functions of the external interface. (2) Features * Up to 32 bit-length (4G bytes space) address output. * Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings. Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type) Page mode ROM/flash memory (2/4/8 page size enabled) Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.) Address/data multiplexed bus (8 bit/16 bit width only) Synchronous memory* (ASIC built-in memory etc.) *: Does not connect to synchronous SRAM. * 8 independent bank (chip select area) settings, each with corresponding chip select output available Each area size can be set in multiples of 64K bytes (from 64K bytes to 2G bytes per chip select area). Each area can be set in any desired area of logic address space (boundaries limited by area size). * The following functions can be independently set for each chip select area. Chip select area enable/disable (no access to prohibited areas) Access timing type for each area, etc. Detailed access timing settings (individual access type settings for wait cycle, etc.) Data bus width setting (8 bit/16 bit) Byte ordering endian setting* (big or little). *: CS0 area available with big endian only. Write prohibited setting (read-only areas) Internal cache loading enable/disable settings Pre-fetch function enable/disable settings Maximum burst length setting (1,2,4,8) * Different detailed timing settings for each access timing type Different settings can be used for each chip select area even for the same access timing type. Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas) Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas) First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas) Different idle, recovery cycles setup delay insertion etc. enabled * Fly-by transfer with DMA enabled Transfer between memory and I/O with 1 access Memory wait cycle can be synchronized with I/O wait cycle during fly-by Hold time can be obtained by delaying transfer access only Specific idle/recovery cycles can be set for fly-by transfer * External bus arbitration using BRQ and BGRNT enabled * Pins not used in external interface can be set for use as general purpose I/O ports
68
MB91307 Series
(3) Block Diagram
Internal address bus Internal data bus
32
32
External data bus
Write buffer
Switch
MUX
Read buffer
Switch
Data block Address block
+1 or +2
External address bus
Address buffer
ASR ASZ Comparator
CS0 to CS7
External pin control block All block control
RD WR0, WR1 AS, BAA BRQ BGRNT RDY
Resisters & controls
(4) I/O Pins These are the external interface pins. (Some pins have dual functions.) < Normal bus interface > A24 to A0, D31 to D16 CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7 AS, SYSCLK, MCLK RD WE, WR0 (UUB) , WR1 (ULB) RDY, BRQ, BGRNT < Memory interface > MCLK LBA ( = AS) , BAA* *: For burst ROM, Flash use 69
MB91307 Series
< DMA interface > IOWR, IORD DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2 (5) Register List
Address 00000640H 00000644H 00000648H 0000064CH 00000650H 00000654H 00000658H 0000065CH 00000660H 00000664H 00000668H 0000066CH 00000670H 00000674H 00000678H 0000067CH 00000680H 00000684H 00000688H 0000068CH *** 000007F8H
31
24 23 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 AWR0 AWR2 AWR4 AWR6
16 15
08 07 ACR0 ACR1 ASR2 ACR3 ACR4 ACR5 ACR6 ACR7 AWR1 AWR3 AWR5 AWR7
00
Reserved Reserved IOWR0 Reserved CSER Reserved Reserved Reserved *** Reserved
Reserved Reserved IOWR1 Reserved CHER Reserved Reserved Reserved *** Reserved (MODR)
Reserved Reserved IOWR2 Reserved Reserved Reserved Reserved Reserved *** Reserved Reserved
Reserved Reserved Reserved Reserved TCR Reserved Reserved Reserved *** Reserved Reserved
000007FCH Reserved
Reserved: This address is reserved, and should always be set to "0." MODR: Cannot be accessed from user programs.
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MB91307 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 0 Max VSS + 4.0 VSS + 2.2 VSS + 4.0 VSS + 4.0 VCC + 0.3 AVCC + 0.3 VCC + 0.3 2.0 20 10 8 100 50 -10 -4 -50 -20 750 +70 +150
Parameter Supply voltage*1 Internal supply voltage Analog supply voltage Analog reference voltage Input voltage*
1
Symbol VCC VCCI AVCC AVRH VI VIA VO ICLAMP ICLAMP IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA TSTG
Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *6 *6 *4 *5 *8 *7 *7 *4 *5 *2 *2 *3 *3 *8
Remarks
Analog pin input voltage Output voltage*1 Maximum clamp current Total maximum clamp current L level maximum output current L level average output current L level maximum total output current L level average total output current H level maximum output current H level average output current H level maximum total output current H level average total output current Power consumption Operating temperature Storage temperature *2 : VCC must not be lower than VSS - 0.3 V.
*1 : The parameter is based on VSS = AVSS = 0 V. *3 : AVCC and AVRH shall never exceed VCC + 0.3 V. Also AVRH shall never exceed AVCC. *4 : Maximum output current determines the peak value of any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. *7 : * Applicable to pins : P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5, PA0 to PA7, P80 to P82, P85, P90 to P97, AN0 to AN3 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 71
MB91307 Series
* Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. *Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits : *Input/Output Equivalent circuits Protective diode
VCC
+B input (0 V to 16 V)
Limiting resistance
P-ch
N-ch
R
*8 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91307 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V) Parameter Supply voltage Analog supply voltage Analog reference voltage Operating temperature Symbol VCC VCCI AVCC AVRH TA Value Min 3.0 1.65 VSS - 0.3 AVSS 0 Max 3.6 1.95 VSS + 3.6 AVCC +70 Unit V V V V C Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91307 Series
3. DC Characteristics
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter "H" level input voltage Symbol VIH VHIS VIL VILS Pin name See note * Input pins other than * See note * Input pins other than * Condition Value Min 0.7 x VCC 0.8 x VCC VSS VSS Typ Max VCC + 0.3 VCC + 0.3 0.25 x VCC 0.2 x VCC VCC Unit V V V V Hysteresis input Hysteresis input Remarks
"L" level input voltage
"H" level output voltage "L" level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance Pull-down resistance
VOH
D16 to D31 VCC = 3.0 V A00 to A25 VCC - 0.5 IOH = - 4.0 mA P6 to PH D16 to D31 VCC = 3.0 V A00 to A25 IOL = 8.0 mA P6 to PH D16 to D31 VCC = 3.6 V A00 to A25 0.45 VV
VOL
0.4
V
ILI
-5
+5
A
RUP RDOWN
12 12
25 25
100 100
k k (4x multiplied) mA 66 MHz operation mA Sleep mode
ICC
150
Supply current
ICCS
50
ICCH
150
A
Stop mode
Input capacitance
CIN
5
15
pF
* : Pins without hysteresis input pins: D16 to D31, RDY, BRQ, INIT
74
MB91307 Series
4. AC Characteristics
(1) Clock Timing Standards (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Clock frequency (3) Clock cycle time Input clock pulse width Input clock rise, fall time Symbol fC tC fC fC tC PWH PWL tCR tCF fCP Internal operating clock frequency fCPP fCPT tCP Internal operating clock cycle time tCPP tCPT Pin name X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 X0 X1 10 10 40 16 0.78*2 0.78*2 0.78
*2
Condition
Value Min 12.5 Max 16.5 60.6 33 33 100 8 66 33 66 1280
*2
Unit MHz ns MHz MHz ns ns ns
Remarks PLL system*1 (self oscillation 16.5MHz,multiplied x4,maximum internal operation 66MHz) Self oscillation (x1/2 frequency input)
External clock
(tCR + tCF)
MHz CPU system MHz Peripheral system MHz External bus system ns ns ns CPU system Peripheral system External bus system
15.2 30.3 15.2
1280*2 1280*2
*1 : When using the PLL, the clock frequency should be around 12.5 to 16.5 MHz. *2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator circuit PLL and a gear ratio of 1/16.
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MB91307 Series
* Clock timing measurement conditions:
tC 0.8 VCC 0.2 VCC PWH PWL
Output pin
C = 50 pF
tCF
tCR
* Warranted operating range
VCC (V)
Power supply
Warranted operating temperature: (TA =0 C to +70 C) fCPP is represented by the shaded area
1.95
1.65
0 0.78
33
Internal clock
66
fCP / fCPP (MHz)
* External/internal clock setting range
(MHz) fCP, fCPT 66
CPU, external bus systems
Internal clock
fCPP
33
Peripheral system
16.5
4:4
2:2
1:2
CPU: Divided ratio for peripherals
Notes : * When using the PLL, the external clock input should be around 16.5 MHz. * Set PLL oscillator stabilization time > 300 s. * The internal clock gear setting should be within the values shown in (1) clock timing standards. 76
MB91307 Series
(2) Clock Output Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Cycle time MCLKMCLK SYSCLKSYSCLK MCLKMCLK SYSCLKSYSCLK Symbol tCYC tCHCL tCLCL Pin name MCLK, SYSCLK MCLK, SYSCLK MCLK, SYSCLK Conditions Value Min tCPT 1/2 x tCYC - 3 1/2 x tCYC - 3 Max 1/2 x tCYC + 3 1/2 x tCYC + 3 Unit ns ns ns Remarks *1 *2 *3
tCYC tCHCL VOH tCLCH VOH
MCLK, SYSCLK
VOL
*1 : tCYC represents the frequency of one clock cycle including the gear period. *2 : The values shown represent standards for x 1 gear period. For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8 respectively. (1/2 x 1/n) x tCYC - 10 *3 : The values shown represent standards for x 1 gear period. Note : tCPT indicates the internal operating clock time. See " (1) Clock Timing Standards".
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MB91307 Series
(3) Reset and Hardware Standby Input Standards (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Hardware standby input time INIT input time (power-on) INIT input time (other than power-on) Symbol tHSTL Pin name VCCI Conditions Value Min tCP x 5 * tCP x 5 Max Unit ns ns ns Remarks
tINTL
INIT
tRSTL, tHSTL, tINTL
HST INIT
0.2 VCC
* : INIT input time (at power-on) FAR, Ceralock : x 215 or greater recommended Crystal : x 221 or greater recommended : Power on X0/X1 period x 2 Note : tCP indicates the clock cycle time. See " (1) Clock Timing Standards".
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MB91307 Series
(4) Normal Bus Access Read/Write Operation (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter CS0 to CS7 setup CS0 to CS7 hold Address setup Address hold Valid address valid data input time WR0 to WR1 delay time WR0 to WR1 minimum pulse width Data setup WRx WRx data hold time RD delay time RD valid data input time Data setup RDtime RD data hold time RD minimum pulse width AS setup AS hold Symbol tCSLCH tCSHCH tASCH tCHAX tAVDV tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tASHCH RD MCLK, SYSCLK, AS RD, D31 to D16 Pin name MCLK, SYSCLK, CS0 to CS7 MCLK, SYSCLK, A23 to A00 MCLK, SYSCLK, A23 to A00 A23 to A00, D31 to D16 MCLK, SYSCLK, WR0 to WR1 WR0 to WR1
WR0 to WR1, D31 to D16
Condition
Value Min 3 3 3 3 tCYC - 3 Max tCYC/2 + 6 tCYC/2 + 6 3/2 x tCYC - 11 6 6 6 6 tCYC - 10
Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * *
tCYC 5 10 0 tCYC - 3 3 3
MCLK, SYSCLK, RD
* : To extend bus time by automatic wait insertion or RDY input, add to this value (tCYC x number of extended cycles). Note : tCYC indicates the cycle time. See " (2) Clock Output Timing".
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MB91307 Series
tCYC BA1 VOH VOH VOH VOH
MCLK, SYSCLK
tASLCH
tASHCH VOH
AS LBA
VOL
tCSLCH
tCSHCH VOH
CS0 to CS7
VOL
tASCH VOH VOL
tCHAX VOH VOL
A23 to A00
tCHRL tRLRH
tCHRH
RD
VOH VOL tRLDV tDSRH tAVDV tRHDX
D31 to D16
VOH VOL
VOH VOL
tCHWL tWLWH
tCHWH VOH VOL
WR0 to WR1
tDSWH
tWHDX
D31 to D16
VOH VOL
Write
VOH VOL
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MB91307 Series
(5) Ready Input Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter RDY setup time MCLK, SYSCLK MCLK, SYSCLK RDY hold time Symbol tRDYS tRDYH Pin name MCLK, SYSCLK, RDY MCLK, SYSCLK, RDY Condition Value Min 10 0 Max Unit ns ns Remarks
tCYC
MCLK, SYSCLK
tCHASL
VOH VOL VOL
VOH
tRDYS
tRDYH
tRDYS tRDYH
RDY
Wait applied
VOH VOL VOL
VOH
RDY
Wait not applied
VOH VOL
VOH VOL
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MB91307 Series
(6) Hold Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter BGRNT delay time Pin floating BGRNTtime BGRNT valid time Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name MCLK, SYSCLK, BGRNT BGRNT Condition Value Min 3 3 tCYC - 10 tCYC - 10 Max 13.5 13.5 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes.
tCYC VOH VOH VOH VOH
MCLK, SYSCLK
BRQ
tCHBGL
tCHBGH VOH tHAHV
BGRNT
tHXAL
VOL
Pins
High-Z
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MB91307 Series
(7) UART Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Serial clock cycle time SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Symbol Pin name tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
SC0 to SC2 SC0 to SC2, SO0 to SO2 SC0 to SC2, SI0 to SI2 SC0 to SC2, SI0 to SI2 SC0 to SC2 SC0 to SC2 SC0 to SC2, SO0 to SO2 SC0 to SC2, SI0 to SI2 SC0 to SC2, SI0 to SI2
Condition
Value Min 8 tCPP Max 80 150
Unit ns ns ns ns ns ns ns ns ns
Remarks
Internal shift lock mode
-80 100 60 4 tCPP 4 tCPP
External shift lock mode
60 60
Notes: * Above ratings are for operation in CLK synchronized mode. * tCPP is the cycle time of the peripheral system clock. * Internal Shift Clock Mode
tSCYC
SC0, SC1
VOL tSLOV
VOH VOL VOH VOL tIVSH tSHIX VOH VOL
SO0, SO1
SI0, SI1
VOH VOL
* External Shift Clock Mode
tSLSH tSHSL VOH VOL tSLOV VOH VOL tIVSH tSHIX VOH VOL VOL VOL
SC0, SC1
SO0, SO1
SI0, SI1
VOH VOL
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MB91307 Series
(8) Timer Clock Input Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0 to TIN2 Condition Value Min 2 tCYCP Max Unit ns Remarks
Note: tCYCP is the cycle time of the peripheral system clock.
TIN0 to TIN2
tTIWH tTIWL
(9) Trigger Input Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter A/D startup trigger input time Symbol Pin name tATGX ATG Condition Value Min 5 tCYCP Max Unit ns Remarks
Note: tCYCP is the cycle time of the peripheral system clock.
tATGX, tINP, tPTG
ATG
84
MB91307 Series
(10) DMA Controller Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter DREQ input pulse width DSTP input pulse width DACK delay time DEOP delay time IORD delay time IOWR delay time Symbol tDRWH tDSWH tCLDL tCLDH tCLEL tCLEH tCLIRL tCLIRH tCLIWL tCLIWH Pin name
DREQ 0 to DREQ2 DSTP 0 to DSTP2 MCLK, SYSCLK, DACK0 to DACK2 MCLK, SYSCLK, DEOP 0 to DEOP2
Condition
Value Min 5 tCYC 5 tCYC Max 6 6 6 6 6 6 6 6
Unit ns ns ns ns ns ns
Remarks
MCLK, SYSCLK MCLK, SYSCLK
85
MB91307 Series
tCYC BA1 VOH BA2 VOH VOL VOL
MCLK, SYSCLK
VOL
tCLDL
tCLDH VOH
DACK0 to DACK2
VOL
tCLEL
tCLEH VOH VOL
DEOP0 to DEOP2
tCLIRL
tCLIRH VOH VOL
IORD
tCLIWL
tCLIWH
VOH
IOWR
VOL
tDRWH
DREQ0 to DREQ2
VOH VOL
tDSWH
DSTP0 to DSTP2
VOH VOL
86
MB91307 Series
(11) I2C Timing (VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter SCL clock frequency (Repeat) "start" condition hold time SDA SCL SCL clock "L" width SCL clock "H" width Repeat "start" condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL "Stop" condition setup time SCL SDA Bus free time between "stop" and "start" conditions Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.0 k, C = 50 pF*1 Condition Standard mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 Max 100 3.45*2 High-speed mode*4 Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 Max 400 0.9*3 Unit kHz s s s s s ns s s
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. *4 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
SDA
tLOW tSUDAT tHDSTA tBUS
SCL
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
87
MB91307 Series
5. A/D Converter Electrical Characteristics
(VCCI = 1.65 V to 1.95 V, VCC = +3.0 V to +3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Resolution Total error Linear error Differential linear error Zero transition error Full scale transition error Conversion time Analog port input current Analog input voltage Reference voltage Supply current Reference voltage supply current Inter-channel variation Symbol VOT VFST IAIN VAIN IA IAH IR IRH Pin name AN0 to AN3 AN0 to AN3 AN0 to AN3 AVRH AVCC AVRH AN0 to AN3 Value Min - 1.5 5.4 * AVss AVss
1
Typ 10 + 0.5 0.1 600 600
Max 10 4.5 3.0 2.5 + 4.5 10 AVRH AVCC 10 *2 10 * 5
2
Unit BIT LSB LSB LSB LSB LSB s A V V A A A A LSB
AN0 to AN3 AVRH - 4.5 AVRH - 1.5 AVRH + 4.5
*1 : At VCC = AVCC = 3.0 V to 3.6 V, VCCI = 1.65 V to 1.95 V machine clock 33 MHz. *2 : Current in CPU stop mode with A/D converter not operating (at VCC = AVCC = AVRH = 3.6 V, VCCI = 1.95 V)
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R Analog input C During sampling : ON Comparator
Note : The values are reference values.
MB91307R/306R MB91V307R
R C 5.0 k (Max) 15 pF (Max) 8.1 k (Max) 10 pF (Max)
88
MB91307 Series
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between external impedance and minimum sampling time External impedance = 0 k to 100 k
100 90 80 70 60 50 40 30 20 10 0 MB91V307R 20 18 16 14 12 10 8 6 4 2 0
External impedance = 0 k to 20 k
MB91V307R
External impedance [k]
External impedance [k]
MB91307R MB91306R
MB91307R MB91306R
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.
* About errors As | AVRH | becomes smaller, values of relative errorsgrow larger.
89
MB91307 Series
Definition of A/D Converter Terms * Resolution Indicates the ability of the A/D converter to discriminate analog variation * Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device's zero transition point (00 0000 000000 0000 0001) and full scale transition point (11 1111 111011 1111 1111) * Differential linear error Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code. [Linear Error]
3FFH 3FEH 3FDH {1 LSB x (N - 1) + VTO}
Actual variation Theoretical
[Differential linear error]
N-1 VFST (measured value)
Actual variation
Digital output
Digital output
N-2
004H 003H 002H
VNT (measured value)
Actual variation Theoretical values
N-1
V(N - 1)T (measured value) VNT (measured value)
001H
N-2
Actual variation
VTO (measured value) AVRH AVRL AVRH
AVRL
Analog input Linear error in digital output N = VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB -1
Analog input
[LSB] [LSB]
Differential linear error in digital output N = 1 LSB = 1 LSB" = VFST - VOT 1022 [V] [V]
AVRH - AVRL 1024
(theoretical value)
VOT : Voltage at which the digital output transitions from "000"H to "001"H. VFST : Voltage at which the digital output transitions from "3FE"H to "3FF"H. VNT : Voltage at which the digital output transitions from (N-1) to N.
90
MB91307 Series
* Total error Expresses the difference between actual and theoretical values as error, including zero transition error, fullscale error, and linearity error.
[Total error]
3FFH
Actual variation
3FEH {1 LSB x (N - 1) + 0.5 LSB 3FDH
1.5 LSB
Digital output
004H 003H 002H
theoretical value
VNT (measured value)
Actual variation
001H 0.5 LSB AVRL AVRH
Analog input
Total error in digital output N =
VNT - {1 LSB" x (N - 1) + 0.5 LSB"} [LSB] 1 LSB" VOT" (theoretical value) = AVRL + 0.5 LSB" [V] VFST" (theoretical value) = AVRH - 1.5 LSB" [V]
VNT : Voltage at which digital output transitions from (N-1) to N.
91
MB91307 Series
EXAMPLE CHARACTERISTICS
(1) Sample output voltage characteristics (TA = +25 C)
Sample output H voltage (VOH) characteristics Sample output L voltage (VOL) characteristics
3.6
Output voltage (V)
0.4
Output voltage (V)
3.4 3.2 3.0 2.8 3.0 3.2 3.4 3.6
Supply voltage (V)
0.3 0.2 0.1 0.0 3.0 3.2 3.4 3.6
Supply voltage (V)
(2) Sample input voltage characteristics (TA = +25 C)
Sample input H/L level characteristics (CMOS) Sample input H/L level characteristics (hysteresis)
3.0
Input voltage (V) Input voltage (V)
3.0 VIH 2.0
2.0 VIH VIL 1.0
1.0
VIL
0.0 3.0 3.2 3.4 3.6 Supply voltage (V)
0.0 3.0 3.2 3.4 3.6 Supply voltage (V)
(3) Sample supply current characteristics
Sample supply current (ICC) characteristics (TA = +25 C, 66 MHz) Sample supply current (ICC) characteristics (VCC = 3.3 V, 66 MHz)
200
Supply current (mA)
200
Supply current (mA)
150 100 50 0 3.0 3.2 3.4 3.6 Supply voltage (V)
150 100 50 0.0 0 25 70 Temperature ( C)
(Continued) 92
MB91307 Series
(Continued)
Sample sleep current (ICCS) characteristics (TA = +25 C, 33 MHz) Sample sleep current (ICCS) characteristics (VCC = 3.3 V, 33 MHz)
Supply current (mA)
50
Supply current (mA)
50 40 30 20
40 30 20
3.0 3.2 3.4 3.6 Supply voltage (V)
0
25 70 Temperature ( C)
Sample A/D supply current (IA) characteristics (TA = +25 C, 33 MHz)
Sample A/D reference current (IR) characteristics (TA = +25 C, 33 MHz)
500
Supply current (A) Supply current (A)
500 400 300 200
400 300 200
3.0
3.2 3.4 3.6 Supply voltage (V)
3.0
3.2 3.4 3.6 Supply voltage (V)
(4) Port resistance characteristics
Sample pull-up resistance characteristics (TA = +25 C) Sample pull-down resistance characteristics (TA = +25 C)
30
Resistance (k)
30
Resistance (k)
25 20 15
25 20 15
3.0 3.2 3.4 3.6 Supply voltage (V)
3.0
3.2 3.4 3.6 Supply voltage (V)
93
MB91307 Series
ORDERING INFORMATION
Part number MB91306RPFV MB91307RPFV MB91V307RCR Package 120-pin, Plastic LQFP (FPT-120P-M21) 135-pin, Ceramic PGA (PGA-135C-A02) Remarks Lead-free package For development tool use
94
MB91307 Series
PACKAGE DIMENSION
120-pin, Plastic LQFP
(FPT-120P-M21)
18.000.20(.709.008)SQ
* 16.00 -0.10 .630 +.016 SQ -.004
90 61
+0.40
Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX 0~8
120 31
"A" 0.100.05 (.004.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 .006
+0.05 -0.03 +.002 -.001
0.600.15 (.024.006)
C
2002 FUJITSU LIMITED F120033S-c-4-4
Dimensions in mm (inches) Note : The values in parentheses are reference values.
95
MB91307 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0502 (c) 2005 FUJITSU LIMITED Printed in Japan

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